`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 			Arizona State University
// Engineer: 			Joe Boeding
// 						Taylor Wood
//
// Create Date:    	14:44:55 03/01/2013 
// Design Name: 		NOR
// Module Name:    	nor_cmos 
// Project Name: 		LAB #1
// Target Devices: 	Xilinx Spartan6 XC6LX16-CS324
// Tool versions: 	Xilinx ISE 14.2
// Description: 		
//		Using "pmos" and "nmos" Verilog switch-level primitives 
//		create a module named "NOR" gate
//
// Dependencies: 		NONE
//
// Revision: 		
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module sig_hys(
    input dir_sig,
    input clk,
    input reset_b,
    output fil_sig
    );
	 
	 parameter TURN_ON_CLOCK_COUNT = 6;
	 parameter TURN_OFF_CLOCK_COUNT = 4;
	 
	 reg [31:0] counter; // counts the complete cycles that dir_sig is high\
	 reg signal=0;
	 
	 always @(posedge clk) begin
			if (~reset_b) begin
				counter <= 0;
				signal <= 0;
			end
			
			else begin
				if (~dir_sig) counter <= 0;
				if (dir_sig || signal) begin
					counter <= counter + 1;
				end
				if (signal) begin
					if (dir_sig) counter <= 0;
					else if (counter == TURN_OFF_CLOCK_COUNT) signal <= 0;
					else signal <= 1;
				end
				else if (counter == TURN_ON_CLOCK_COUNT) begin
					counter <= 0;
					signal <= 1;
				end	
			end 
	end
	 
	assign fil_sig = signal;
	 
endmodule